Memory devices have traditionally been accessed by a relatively standard set of control signals that are used by all manufacturers. For example, dynamic random access memories (DRAMs) have traditionally been accessed by a row address strobe (RAS) signal, a column address strobe (CAS) signal, and a write enable (WE) signal. These signals were used to control the timing of the internal circuitry on the memory, and the memory generally performed asynchronously with respect to any other system clock signals. Recently, synchronous DRAMs have also become popular.
Generally, a memory controller initiates a DRAM access by providing a row address to the DRAM and activating RAS. After the DRAM has latched the row address, the memory controller provides a column address to the DRAM and activates CAS. Once the DRAM latches the column address, it either provides the data to a data bus or latches data present on the data bus as appropriate. To conclude the cycle, the memory controller deactivates both RAS and CAS. In response to the deactivation of RAS, the DRAM precharges all the rows in preparation for a subsequent access to another row.
There are two important variations to basic DRAM timing known in the prior art. The first variation is known as burst page mode. During a burst page mode access, the memory controller begins the access by providing the first address of a group of related accesses to the DRAM. For example, the addresses can be consecutive addresses after the first address, or can be ordered in a predefined manner. For example, the addresses may be clustered modulo m around the first address, as disclosed by U.S. Pat. No. 4,799,199. The DRAM begins the burst access by activating a word line corresponding to the selected row. Since multiple columns of data are located along the selected row, subsequent accesses in the burst proceed without the row being deselected. Thus the memory controller keeps RAS active during the burst cycle and only deactivates CAS to select different column. DRAMs are able to perform burst page mode accesses faster than a corresponding number of non-burst accesses because it eliminates unnecessary repetitive decoding of the same row address. However, burst page mode does not allow two or more accesses to the same row which are not in the predetermined order.
Another variation is known as full page mode. In full page mode systems, a subsequent address is compared to a prior address to determine whether the subsequent access is to the same row, also known as the page. If the subsequent address is to the same page, the memory controller does not need to perform a redundant row selection by providing the same row address to the DRAM and activating RAS. Thus the memory controller keeps RAS active and avoids the row address selection cycle for any subsequent access to the same row. However in order to do the comparison, the memory controller implementing full page mode cannot begin a precharge of the DRAM by deactivating RAS until the second address is available and the address comparison is complete. The additional precharge time required for full page accesses usually offsets the advantage of accessing addresses on the same row in an arbitrary order. Another disadvantage of full page mode is that it does not work with extended data out (EDO) memories. EDO memories keep data valid on data output pins for an extended period, after CAS has been deactivated. Since full page mode memories require the subsequent address to be valid to determine whether to deactivate RAS, the next cycle begins and may even cause contention on the data bus.
What is needed is a controller for dynamic memories which allows full page accesses, but without the precharge penalty and with a minimum of circuit area. The present invention provides such a memory controller and a related method, and its features and advantages will be further described with reference to the drawings and the accompanying description.